The present invention relates to a method for manufacturing semiconductor devices and, more particularly, to a method for manufacturing semiconductor memory devices each of which includes an MNOS-type transistor and an MNOS-type capacitor or includes an MOS-type transistor and an MNOS-type capacitor.
There are two primary types of semiconductor memory devices, a static type and a dynamic type. The static-type semiconductor memory device can generally operate at high speed. On the other hand, since the dynamic-type semiconductor memory device requires a small cell area, it is generally suitable for structuring memories of large capacity.
Recently, a dynamic-type memory element which is composed of a single transistor and a single capacitor and which has a minimum cell area has been widely used. The equivalent circuit of such a cell is shown in FIG. 1. In FIG. 1, the transistor, the capacitors, a bit line and a word line are depicted by T, C, B and W, respectively.
The conventional method of manufacturing the semiconductor memory shown in FIG. 1 will be described with reference to FIG. 2. In FIG. 2 a memory cell including an N channel MOS transistor having double crystal silicon layers and a capacitor is used as an example of the semiconductor memory element because the memory cell of the above type has wide applicability and is convenient for comparison with the present invention.
As shown in FIG. 2, a P-type silicon substrate 1 is used and thick oxide layers 2 are formed using a photographic method on portions of the surface of the substrate other than surface portions on which a drain gate and a capacitor are to be formed so as to provide electrical separation between unit elements. Following this, a thin oxide film 3 is formed on the exposed surface portion of the substrate as shown in FIG. 3. Thereafter, a polycrystalline silicon film 4 having a suitable thickness is epitaxially formed over the wafer.
In order to improve the electric conductivity of the polycrystalline silicon film 4, n-type impurities such as phosphorus are added thereto by thermal diffusion. An insulative layer 8' may be deposited on the impurity containing polycrystalline silicon layer 4 if necessary. Portions of the polycrystalline silicon film 4 and the insulative layer 8', if necessary, may be removed through a resist mask by plasma or chemical etching with portions left remaining in which the capacitor is to be formed.
After removing a portion of the oxide film 3 in an area in which a transfer transistor is to be formed, a thin oxide film 5 which is used as a gate oxide film of the transistor is formed in the same area as shown in FIG. 4. Thereafter, a polycrystalline silicon layer 6 is again formed using a method such as the CVD method to form a gate electrode of the transistor as shown in FIG. 4. Then by using the polycrystalline silicon layers 4 and 6 as masks, n-type impurities are introduced into the silicon substrate 1 by a suitable method such as thermal diffusion or ion injection to form a drain region 7.
With reference to FIG. 5, after an oxide layer 8 is formed over the entire surface of the wafer by a suitable method such as the CVD method, a contact hole 9 for the gate electrode is formed using a photographic method in the oxide film 8 through which a metal contact layer 10 formed of a material such as aluminum which is vapor deposited. Then, an interconnection layer of aluminum which is connected to the gate electrode is formed using a photographic method to obtain a word line W. FIG. 6 is a plan view of the memory cell thus produced. As shown in FIG. 6, the contact hole 9 extends over two memory cells.
It is well known that the higher the element density required in a MOS LSI device the smaller must be the size of an individual memory cell. With this requirement, the size of contact hole 9 should be made smaller as the element density increases. Unfortunately, a reduction in the size of the contact hole produces other problems. Namely, it is very difficult as a practical matter to form many small contact holes with a high precision and there is a high probability of damage to the interconnection material, that is the aluminum layers, due to the presence of a step existing at an edge portion of the contact hole. In order to eliminate the latter problem, a large amount of some material such as phosphorus may be added to the oxide layer 8 and the sharp edge portion of the contact hole may be rounded. Use of such techniques, however, enlarges the area of the contact hole thereby limiting the reduction of the cell area. Further, with a reduction of the contact hole size, the contact resistance between the polycrystalline silicon substrate and the aluminum electrode becomes large causing a degradation of the electrical characteristics of the cell.
Since a conventional memory cell has three formed layers, namely, a pair of polycrystalline silicon layers and an aluminum layer, there are many stepped portions in the cell. These stepped portions may cause damage to the interconnection layers. This is especially true when the interconnections include thin aluminum leads. In this connection, the electric insulation between the first polycrystalline silicon layer and the second polycrystalline silicon layer is relatively poor because the thickness of the oxide layer existing therebetween is at most on the same order of thickness as the gate oxide layer.
Furthermore, the capacitance between the electrodes, which should be as small as possible, is rather large. In addition to the above mentioned defects in the conventional semiconductor memory device, the thinner the thickness of the oxide layer between the first polycrystalline silicon layer and the silicon layer corresponding to the capacitor portion the larger will be the cell size. Therefore, possible small defects in the thin oxide layer may provide passage for leakage current resulting in damage to the cell.